Precise analogue synapse for Kohonen feature maps

A plastic medium-term analogue memory or synapse is presented that fulfils the stringent specifications necessary fory the Kohonen algorithm. The principle is based on a switched capacitor-like technique implementing a variable time-constant integrator. The memory leakage standard deviation is 2mV/s at room temperature and the learning gain can be varied over two decades. Its differential structure leads to good PSRR and charge injection cancellation. The total synapse area is 1/16 mm² using a 3 ¿m self-aligned contact single-metal CMOS technology. Measurement results of a test chip are also presented.