Bit_Serial Architecture for the Calculation of the Two Dimensional DCT

We present an architecture for the calculation of the Two Dimensional Discrete Cosine Transform and its Inverse that admits a high data rate. It is based on the row-column decomposition, the use of a fast algorithm, serial digit arithmetic and redundant coding. The critical path is set by the delay of a multiplexer plus a binary adder with as many digits as the width of the serial digits to be processed. We discuss its implementation for processing 8 bit 8×8 pixel blocks or 12 bit coefficients. Its implementation using standard cell 1 microm CMOS technology presents a 100MHz data rate and a core area of 42mm².