Title :
Use Of World Wide DSP Low Power 0.72 μm "S3" Standard Cell Library For Dedicated GSM Peripherals
Author :
Aqachmar, Mustapha ; Boutaud, Frederic
Author_Institution :
DSP-ASP MS21 Texas Instruments, 06271 Villeneuve Loubet (33).93.22.20.48, aqachmar@tif.ti.com
Abstract :
This paper describes how the "S3" standard-cell library helps optimising the speed of circuits; and reduce their power dissipation and the silicon area they occupy. The "S3" standard-cell library is designed and used with automated compilers to produce blocks layout with a performance close to one of layouts produced by hand. The cells are interconnected by rows and overall layout nevertheless benefits of regularity in placement inherent to such compilers. The "S3" Standard-cell library is used at world-wide level by TI-DSP design centers and by selected customers to develop DSP cores and peripherals for applications like cellular phone, DTAD, HDD, and modem. This library was used to create modular and reusable peripherals which were integrated on several low voltage high performance circuits like standard DSP such TMS320C56, 320C57, 320C542.
Keywords :
Delay effects; Digital signal processing; GSM; Integrated circuit interconnections; Libraries; Logic arrays; Logic circuits; Signal design; Silicon; Timing;
Conference_Titel :
Solid-State Circuits Conference, 1995. ESSCIRC '95. Twenty-first European
Conference_Location :
Lille, France
Print_ISBN :
2-86332-180-3