A High Rate VLSI circuit For the radix-2 Fast Hartley Transform

In many applications, the Discrete Hartley Transform (DHT) is a suitable substitute for the Discrete Fourier Transform (DFT) for a real-valued signal. Certain digital signal processing algorithms, such as adaptive filtering algorithms, require a large number of DHT operations to be performed in a short time. This can interfere with real time implementation of the algorithm. One way of overcoming this difficulty may be the implementation of the algorithm on a specific VLSI architecture, into which a specific FHT operator is integrated, thus avoiding communication with an auxiliary DSP. In this paper we present a high speed VLSI architecture for the fixed point radix-2 FHT algorithm. This architecture has an optimized area and allows a much shorter execution time than on General Purpose DSP (GPDSP) chips.