Semiconductor Technologies with Reduced Dimensions

In the last years the complexity of integrated circuits has grown exponentially. This growth has been achieved primarily by increasing the chip area, by reducing the linewidths, and last but not least by improving devices and circuits. This paper deals with the methods and problems associated with linewidth reduction. It is the aim of the paper to present to the circuit engineer simplified models of typical results which allow him to consider these results for future circuits and assist him in his cooperation with technological engineers and device physicists.