• DocumentCode
    517163
  • Title

    A Multiplier-Accumulator Macro for a 45 MIPS Embedded RISC Processor

  • Author

    Yano, Naoka ; Ootaguro, Yukio ; Sugeno, Yukio ; Ueno, Maki ; Muroya, Yukinori ; Aramaki, Tsuneo

  • Author_Institution
    TOSHIBA Corporation, Kawasaki, Japan
  • fYear
    1995
  • fDate
    19-21 Sept. 1995
  • Firstpage
    174
  • Lastpage
    177
  • Abstract
    This paper describes a high speed and area effective multiplier-accumulator for an embedded RISC processor. The point is to utilize a multiplier array and the Booth´s encoder twice in a cycle. This multiplier-accumulator can execute one multiply-add operation (32bit multiplication followed by 64bit addition) per cycle at 50MHz. The area is 2.35mm2 with 0.4¿m CMOS technology.
  • Keywords
    CMOS technology; Clocks; Delay; Engines; Filters; Information systems; Microelectronics; Microprocessors; Reduced instruction set computing; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1995. ESSCIRC '95. Twenty-first European
  • Conference_Location
    Lille, France
  • Print_ISBN
    2-86332-180-3
  • Type

    conf

  • Filename
    5469298
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=517163