175 MS/s, 6 Bit, 160mW, 3.3V CMOS A/D Converter

The highest sampling rates in A/D converters are obtained with flash type architectures. At very high speeds no offset cancelling techniques can be used, and hence the accuracy of the A/D converter is based on the matching performance of the technology. Knowledge on the matching behaviour of the circuit components extends the design of high speed A/D converters towards a power-accuracy trade-off. This is demonstrated in the design of a 175 MS/s, 6 bit interpolating A/D converter in 0.7 ¿m digital CMOS technology. The circuit operates at 3.3V power supply and consumes 160 mW.