A Digital FM Demodulator Chip based on Measurement of IF-Signal´s Period

A fully digital, low-power FM demodulator circuit is presented. The function of the demodulator is based on measuring the cycle time of amplified IF signal with subnanosecond resolution which is achieved by combining a 20MHz counter with a 64 tap voltage-controlled delay line interpolator. The main features of this new detector are a very stable demodulation gain and low and known distortion. The demodulator is implemeted in a 1.2 ¿m BiCMOS process and tested in a mobile telephone environment at an IF frequency of 455kHz and maximum deviation of 5kHz. Test results showed an in-system performance of SNR over 65dB, SINAD of 40dB and sensitivity down to ¿105 dBm input levels. The demodulator consumes 2mA from a single 5V supply.