High Resolution Digitally Controlled Frequency Multiplier with Very Large Programmable Multiplication Factor

This paper presents a high resolution Frequency Multiplier (FMUL) with the ability to multiply frequency with a high multiplication factor. It was designed for chip-sets that use a real time clock (32,768Hz) for power-save operation, and an additional high-frequency oscillator, in the range of 40MHz, for regular operation. Using the FMUL enables to spare the need for the additional high-frequency oscillator. The chip will be driven by a single clocking source - the low-frequency oscillator. The FMUL is almost fully digital, its output frequency resolution is 100ppm, and the multiplication factor is a programmable ratio of the form N/M, that can vary between 1 and 16,383. The high-frequency at the FMUL´s output may be up to 200MHz. The circuit is designed to work with 2.5-5.5v supply voltage. It is implemented in a standard 0.8um N-well CMOS process, and its area is 750mil².