Title :
A Portable Clock Multiplier Generator using Digital CMOS Standard Cells
Author :
Combes, Michel ; Dioury, Karim ; Greiner, Alain
Author_Institution :
Institut Blaise Pascal, Laboratoire MASI, Couloir 55-65, 2ÿme étage, Université Pierre et Marie Curie (P6) CNRS URA 818, 4 place Jussieu, 75252 Paris Cedex 05, FRANCE. Phone: 44 27 30 43, Fax: 44 27 62 86
Abstract :
This paper presents a circuit fabricated to test a new method of clock frequency multiplication. This new approach uses a digital CMOS process in order to implement the delay locked loop. This multiplier does not require external components. Moreover it is generated by a parameterized generator written in C which relies on a portable digital standard cell library, for automatic place and route. In 1¿m CMOS process a 170Mhz clock signal has been obtained from a 8.5Mhz external clock with a measured jitter lower than 300ps.
Keywords :
CMOS digital integrated circuits; CMOS process; Circuit testing; Clocks; Delay effects; Fabrication; Flip-flops; Frequency conversion; Phase locked loops; Software libraries;
Conference_Titel :
Solid-State Circuits Conference, 1995. ESSCIRC '95. Twenty-first European
Conference_Location :
Lille, France
Print_ISBN :
2-86332-180-3
