Analog VLSI Data Converters - The First 10 Years

Commercial analog integrated circuits crossed the VLSI threshold of 10,000 transistors back in 1984. Today´s analog VLSI circuits routinely surpass the million transistor complexity level. This Moore´s Law increase in integration, combined with the analog designer´s tradition of cleverness, is responsible for most of the decade´s performance improvement in state-of-the-art data converters. Moore´s Law applies to MOS technologies, and scaled MOS processes have their limitations. Low frequency noise of the scaled MOSFET is a minor irritation, as 1/f noise is always vulnerable to architectural attack. Curiously, the world´s most accurate low frequency data converters have long been produced with some of solid-state electronics´ worst low frequency devices. A greater concern is the ever-decreasing supply voltage for analog circuits, but increasing capacitor values and device speeds compensate for this loss. VLSI data converters continue to improve in the 5V era at their traditional 2dB/year rate. Reduced supply voltages do tend to push ADCs ever closer to transducers, and most common transducers produce only millivolt signal swings. The sections which follow survey the evolution of VLSI data converter architecture over the last 10 years and offer some predictions for the next ten years. It´s reasonable to speculate that data converter dynamic range improvement may slow down as we approach, say, the noise of a 50Ω resistor in a bandwidth of half the sampling frequency, but such quasifundamental limits lie beyond the next decade.