Title :
A 1.75-GHz/3-V Dual-Modulus Divide-by-128/129 Prescaler in 0.7-μM CMOS
Author :
Craninckx, Jan ; Steyaert, Michiel
Author_Institution :
Katholieke Universiteit Leuven, ESAT-MICAS, Kard. Mercierlaan 94, B-3001 Heverlee, Belgium
Abstract :
A dual modulus divide-by-128/129 prescaler has been developed in a 0.7-μm CMOS technology. A new circuit technique enables to limit the high-speed section of the prescaler to only one divide-by-2 flipflop. That way a dual-modulus prescaler with the same speed as an asynchronous divider can be obtained. The measured maximum input frequency of the prescaler is up to 1.75 GHz, and the power consumption is 8 mA from a single 3-V power supply.
Keywords :
CMOS technology; Circuits; Delay; Energy consumption; Frequency control; Frequency conversion; Frequency synthesizers; Master-slave; Phase locked loops; Power measurement;
Conference_Titel :
Solid-State Circuits Conference, 1995. ESSCIRC '95. Twenty-first European
Conference_Location :
Lille, France
Print_ISBN :
2-86332-180-3