VHDL Model of an Array-of-Array Multiplier Implemented in CMOS Sea-of-Gates

We have generated parametric VHDL descriptions for two parallel multiplier architectures: the array-of-array multiplier developed at Delft University, and the classical array multiplier. Using the VHDL descriptions we have synthesized 32×32-bit signed (two´s complement) multipliers, and we have implemented two prototypes in 1.6¿m CMOS fishbone sea-of-gates. The implementation was aimed to compare the two architectures in terms of speed and area. The implemented array-of-array multiplier is 6% larger and 1.7 times faster than the array multiplier. The array-of-array design contains 48036 transistors, and the longest multiplication time was measured as 42 ns.