• DocumentCode
    517275
  • Title

    A Sub 10 nS, 20 nA Stand-by Current Full CMOS 4KÃ\x978 Dual Port Memory

  • Author

    Martinez, R. ; Delaunay, P. ; Danckaert, J.Y.

  • Author_Institution
    MATRA M.H.S., La Chantrerie, C.P. 3003, 44 087 NANTES CEDEX 03 FRANCE. Phone: (33) 40.18.18.18.
  • fYear
    1995
  • fDate
    19-21 Sept. 1995
  • Firstpage
    362
  • Lastpage
    365
  • Abstract
    A sub 10 ns, 20 nA stand-by current, full CMOS, 4k×8 DUAL PORT RAM has been developed. It was fabricated using the 0.6¿m, double metal MHS´ SCMOS technology. The use of a full bulk CMOS 8 T memory cell allows a very low stand-by current. The memory cell area is 11.8 * 10.2 ¿m2 with a chip size of 3.5 * 4.85 mm2. This DPRAM has been designed in order to fit high speed product market requirements. The typical performances are a chip select access time of 9.5 ns (both ports active), a stand-by current of less than 20 nA and an operating current of 250 mA for a 65 MHz cycle.
  • Keywords
    Application software; CMOS technology; Central Processing Unit; Chromium; Circuits; Military computing; Preamplifiers; Random access memory; Read-write memory; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1995. ESSCIRC '95. Twenty-first European
  • Conference_Location
    Lille, France
  • Print_ISBN
    2-86332-180-3
  • Type

    conf

  • Filename
    5469411