Title :
Very High Density Placement and Routing for 1-to-N-Layer Gate Arrays using Gatesnake
Author :
Buset, Oscar ; Duchene, Philippe ; Declercq, Michel
Author_Institution :
Ecole Polytechnique Fédérale de Lausanne, DE-LEG, ELB-Ecublens, CH-1015 Lausanne, SWITZERLAND
Abstract :
We present a new program, GateSnake, for cell-based place and route on gate arrays. GateSnake is currently used with 1 and 2 metal layer arrays. For the single-metal case, comparisons with manual layout (the method used before our tool was ready) show an improvement in density of 15 %. For the dual metal case, comparisons against the incumbent place and route solution (2 popular commercial programs) show density increases of 10 and 20%.
Keywords :
BiCMOS integrated circuits; Costs; Electronic design automation and methodology; Libraries; Production; Routing; Sun; Time to market; Wires;
Conference_Titel :
Solid-State Circuits Conference, 1995. ESSCIRC '95. Twenty-first European
Conference_Location :
Lille, France
Print_ISBN :
2-86332-180-3
