Title :
Low-Power Circuit Techniques for High-Speed ECL SRAMs
Author :
Elrabaa, M.S. ; Elmasry, M.I.
Author_Institution :
Student Member, IEEE, VLSI Research Group, Dept. of E&CE, University of Waterloo, Waterloo, Ontario, Canada.
Abstract :
Novel circuit techniques that reduce the total power of BiCMOS/ECL SRAMs by over 40% while preserving their speed are reported. These include techniques to reduce the DC power of the input buffers and Wired-OR (W-OR) predecoderes, the activated memory block, and the sensing circuits. Techniques such as gated-active-pull-down W-ORing, self-resetting drivers and unclocked latched sense amplifiers are used.
Keywords :
BiCMOS integrated circuits; Decoding; Delay; Driver circuits; MOS devices; Output feedback; Plastic packaging; Resistors; Very large scale integration; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1995. ESSCIRC '95. Twenty-first European
Conference_Location :
Lille, France
Print_ISBN :
2-86332-180-3
