DocumentCode
517281
Title
A Survey of MOS Logic Simulation Tools
Author
Heydemann, M.H.
Author_Institution
CISI, BP 24, 91190 Gif-sur-yvette, France
fYear
1983
fDate
21-23 Sept. 1983
Firstpage
19
Lastpage
24
Abstract
This paper aims at providing circuit designers with a better understanding of the respective capabilities and limitations of both gate-level and switch-level logic simulation of MOSLSI designs. It presents a brief introduction to the underlying mathematical models, and suggests further research and developments in this area.
Keywords
Analytical models; Brain modeling; Circuit simulation; Computational modeling; Integrated circuit interconnections; Logic circuits; Logic design; Logic testing; Mathematical model; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1983. ESSCIRC '83. Ninth European
Conference_Location
Lausanne, Switzerland
Print_ISBN
2-88074-021-5
Type
conf
Filename
5469418
Link To Document