• DocumentCode
    517283
  • Title

    A Fast 16 Bit NMOS Parallel Multiplier

  • Author

    Lerouge, C. ; Girard, P. ; Colardelle, J. ; Obermeier, C.

  • Author_Institution
    Laboratoire Central de Télécommunications, Vélizy, France
  • fYear
    1983
  • fDate
    21-23 Sept. 1983
  • Firstpage
    29
  • Lastpage
    32
  • Abstract
    A fast (120ns) and low power (200 mW) NMOS multiplier is described. It contains a non-technology dependent 16 × 16 parallel array. Silicon area is 5 mm2.
  • Keywords
    Adders; Array signal processing; Delay effects; Integrated circuit interconnections; Logic; MOS devices; Propagation delay; Signal design; Silicon; Tellurium;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1983. ESSCIRC '83. Ninth European
  • Conference_Location
    Lausanne, Switzerland
  • Print_ISBN
    2-88074-021-5
  • Type

    conf

  • Filename
    5469420
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=517283