Performance Analysis of NMOS for Higher Speed and Low Power Applications

Integrated circuits based on low supply voltage and subthreshold operations of NMOS devices are very attractive for low power applications. An effective way to reduce supply voltage and resulting in power consumption without losing the circuit performance of NMOS is to increase the drive current of NMOS. This paper reports the scaling analysis of NMOS from deep-submicron to nanometer technologies, in which channel length has been scaled down from 600nm to 90 nm. For simulation, ATLAS device simulator is used, by using the models LAMBARDI (CVT) mobility model and fixed Shockley-read-hall model recombination model. Simulation result depicts that threshold voltage is 0.26V at 600nm, 0.04V at 180nm and 0.01V at 90nm so nanometer range NMOS devices can be very attractive for low power and subthreshold operations.