Design of a branch prediction unit of a microprocessor based on superscalar architecture using VLSI

In the field of microprocessors, speeds of processor doubles in every 18 months as, new microprocessors are always being designed using more and more advanced features. So, it´s always a challenge to design a new microprocessor with faster execution speed. In this paper microarchitecture of superscalar processor is to be designed using VLSI. This Proposed design is based on the rigorous research done through simulation of superscalar architecture using Simplescalar tool. The research was concentrated in three areas 1.Data dependence 2.Control dependence 3.Memory latency Various results were taken for several benchmarks in areas of operating system, database, and mathematics etc using `C´ language for different combinations of parameters. We have developed an optimum model which would give a consistent performance in all the above areas. Among the three areas control dependence is critical to get better performance. So, we are concentrating on the design of a 1-level and 2-level branch prediction scheme of control dependence area. The branch prediction unit will be externally interfaced to a IP core through VLSI technique. By verifying the performance of the branch prediction unit using FPGA we are trying to find out an optimum branch prediction unit for superscalar processor.