Fast evaluation-based algorithm for fixed-outline floorplanning

Floorplanning is a very crucial step in modern VLSI designs. It dominates the top-level spatial structure of a chip and initially optimizes the interconnections. Thus a good floorplan solution among circuit modules definitely has a positive impact on the placement, routing and even manufacturing. In this paper, we propose an efficient approach for the evaluation of the insertion points. The proposed method evaluates 2n insertion points, instead of all (n + 1)² insertion points as did in the state-of-the-art. The proposed techniques can be integrated into the general simulated annealing algorithm, resulting in a fast algorithm for floorplanning. Experimental results show that, the state-of-the-art can be improved up to 37% in terms of running time, without loss of success rate. In addition, our algorithm is comparable to the state-of-the-art in terms of wirelength.