A reconfigurable and high precision VLSI architecture for Fast Fourier Transform

Author

Zhizhe, Liu ; Shun, Zhong

Author_Institution

Sch. of Inf. & Electron., Beijing Inst. of Technol., Beijing, China

Volume

4

fYear

2010

fDate

16-18 April 2010

Abstract

A reconfigurable and high precision FFT architecture is presented in this paper. The mixed radix-4/2 butterfly core is used in this architecture and the system can be configured as N=2n(n=5,6,7,8,9,10,11,12) size FFT. A data scaling approach is proposed and the Signal-to-Quantization Noise Radio (SQNR) can achieve up to 72.45dB when the system works at the 4096-point mode. Implementation of the proposed FFT architecture is under 0.18-μm signal-poly six-metal SMIC CMOS process. The power dissipation is 45mW at 20MHz.

Keywords

CMOS integrated circuits; VLSI; fast Fourier transforms; hypercube networks; quantisation (signal); reconfigurable architectures; SQNR; VLSI architecture; data scaling; fast Fourier transform; frequency 20 MHz; high precision FFT architecture; mixed radix-4/2 butterfly core; power dissipation; reconfigurable architecture; signal-poly six-metal SMIC CMOS process; signal-to-quantization noise radio; size 0.18 mum; CMOS process; Discrete Fourier transforms; Fast Fourier transforms; Fourier transforms; Hardware; Memory architecture; OFDM; Power dissipation; Signal processing; Very large scale integration; Fast Fourier Transform (FFT); Reconfigurable; mixed-radix;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Engineering and Technology (ICCET), 2010 2nd International Conference on

Conference_Location

Chengdu

Print_ISBN

978-1-4244-6347-3

Type

conf

DOI

10.1109/ICCET.2010.5485498

Filename

5485498