• DocumentCode
    5188
  • Title

    Symbolic Model Checking for Incomplete Designs with Flexible Modeling of Unknowns

  • Author

    Nopper, T. ; Scholl, C.

  • Author_Institution
    Dept. of Comput. Sci., Univ. of Freiburg, Freiburg, Germany
  • Volume
    62
  • Issue
    6
  • fYear
    2013
  • fDate
    Jun-13
  • Firstpage
    1234
  • Lastpage
    1254
  • Abstract
    We consider the problem of checking whether an incomplete design (i.e., a design containing "unknown parts", so-called Black Boxes) can still be extended to a complete design satisfying a given property or whether the property is satisfied for all possible extensions. There are many applications of property checking for incomplete designs, such as early verification checks for unfinished designs, error localization in faulty designs and the abstraction of complex parts of a design in order to simplify the property checking task. To process incomplete designs we present an approximate, yet sound algorithm. The algorithm is flexible in the sense that for every Black Box a different approximation method can be chosen. This permits us to handle less relevant Black Boxes (in terms of the property) with larger approximation and thus faster, whereas we do not lose important information when the possible effect of more relevant Black Boxes is modeled by more exact methods. Additionally, we present a concept to decide exactly whether Black Boxes with bounded memory can be implemented so that they satisfy a given property. This question is reduced to conventional symbolic model checking. The effectiveness and feasibility of the methods is demonstrated by a series of experimental results.
  • Keywords
    approximation theory; binary decision diagrams; formal verification; approximation method; black box; bounded memory; error localization; exact method; faulty design; incomplete design; property checking; symbolic model checking; unfinished designs; verification checks; Algorithm design and analysis; Approximation methods; Boolean functions; Computational modeling; Data structures; Integrated circuit modeling; Logic gates; BDDs; Black Boxes; Symbolic model checking; abstraction; approximation; incomplete designs; verification;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.2012.53
  • Filename
    6158639