A comparative analysis of behavioral simulation for third-order cascaded multi-bit Delta-Sigma modulator with interstage feedback paths

With the advance in semiconductor technology, the integration of digital and analog circuits on the same die becomes ubiquitous. The increasing demand of mixed signal integrated circuits drives the higher resolution for Digital-Analog circuits as well as Analog-Digital modulators. In this work, we perform a comprehensive analysis of an existing architecture of cascaded multi-bit Delta-Sigma Third-order modulator with interstage feedback paths using behavioral simulation. The model has been proofed mathematically in reducing the performance degradation by the DAC nonlinearity errors by Su and Chao. The contributions of this paper are as follows. First, we demonstrate that the DAC nonlinearity errors are the most prominent noise in the system based on the behavioral simulation. Second, the mathematical model is compared with the behavioral simulator for both ideal case (noises other than DAC noise are suppressed) and when other non-idealities are introduced. Finally, analysis effects of the DAC nonlinearity error parameters of each modulator stage are studied.