Title :
Parallel LFSR reseeding for mixed-mode BIST
Author :
Kongtim, P. ; Reungpeerakul, T.
Author_Institution :
Dept. of Comput. Eng., Prince of Songkla Univ., Hat Yai, Thailand
Abstract :
In this paper, a novel parallel LFSR reseeding technique for mixed-mode BIST that is suitable and applicable to a multiple scan chain design. This approach can be applied to generate test cubes that detect Random Pattern Resistant (RPR) faults. A multiple test vector is used to guide the LFSR in order to generate target test cube at the application time. The encoded test seed is solved by using a system linear equation. Experimental results have been discussed by performing the largest ISCAS 89 benchmark circuits. Advantages: 100% test coverage, reduction of test application, reduction of test data storage, requiring few additional hardware, high fault coverage as intended by the deterministic test, and capability to generate any deterministic test cubes without proportional to the largest number of specified bits.
Keywords :
built-in self test; logic testing; shift registers; vectors; RPR fault; linear feedback shift register; mixed-mode BIST; multiple scan chain design; multiple test vector; parallel LFSR reseeding technique; random pattern resistant; system linear equation; Benchmark testing; Built-in self-test; Circuit faults; Circuit testing; Equations; Fault detection; Memory; System testing; Test pattern generators; Vectors;
Conference_Titel :
Electrical Engineering/Electronics Computer Telecommunications and Information Technology (ECTI-CON), 2010 International Conference on
Conference_Location :
Chaing Mai
Print_ISBN :
978-1-4244-5606-2
Electronic_ISBN :
978-1-4244-5607-9
