• DocumentCode
    519164
  • Title

    A high-throughput and small ADALINE based adaptive noise canceller for 50-hz noise in surface Electromyography on an FPGA

  • Author

    Chewae, Sainan-Abeedin ; Jindapetch, Nattha ; Phukpattaranont, Pornchai

  • Author_Institution
    Dept. of Electr. Eng., Prince of Songkla Univ., Hat Yai, Thailand
  • fYear
    2010
  • fDate
    19-21 May 2010
  • Firstpage
    146
  • Lastpage
    150
  • Abstract
    This paper presents a design of an adaptive noise canceller for 50-Hz noise in surface Electromyography (SEMG). An adaptive linear neural network (ADALINE) filter without reference signal from the outside was designed into three formats: a 32-bit floating-point format, a 32-bit fixed-point format, and a 16-bit fixed-point format. In additions, the 16-bit fixed-point format was optimized for area using the resource-sharing technique that considers the interconnect complexity. The design and the simulation were performed by using Matlab Simulink and Xilinx Accel DSP Toolbox to find the most optimized circuit on Xilinx Spartan-3 (XC3S400-4TQ144). The filter efficiency was measured by the correlation coefficient and the normalized mean square error (NMSE). From the results, the 10-tap ADALINE implemented in the 16-bit Q0.15 fixed-point format can achieve the throughput of 1.656 MSPS and the area of three multipliers, 1831 LUTs, and 858 flip-flops, whereas the signal quality is the same as the others.
  • Keywords
    adaptive filters; electromyography; field programmable gate arrays; fixed point arithmetic; flip-flops; floating point arithmetic; interference suppression; medical signal processing; neural nets; ADALINE based adaptive noise canceller; FPGA; Matlab Simulink; XC3S400-4TQ144; Xilinx Accel DSP Toolbox; Xilinx Spartan-3; adaptive linear neural network filter; correlation coefficient; fixed-point format; flip-flops; floating-point format; frequency 50 Hz; interconnect complexity; normalized mean square error; optimized circuit; resource-sharing technique; storage capacity 16 bit; storage capacity 32 bit; surface electromyography; Adaptive filters; Adaptive systems; Circuit simulation; Electromyography; Field programmable gate arrays; Integrated circuit interconnections; Neural networks; Noise cancellation; Nonlinear filters; Signal design; ADALINE; Adaptive noise cancellation; FPGA; LMS;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical Engineering/Electronics Computer Telecommunications and Information Technology (ECTI-CON), 2010 International Conference on
  • Conference_Location
    Chiang Mai
  • Print_ISBN
    978-1-4244-5606-2
  • Electronic_ISBN
    978-1-4244-5607-9
  • Type

    conf

  • Filename
    5491513