Title :
Electrical and structural properties of ge metal-oxide-semiconductor devices with Pt/HfO2 gate stacks
Author :
Choi, Chel-Jong ; Shin, Kyu-Sang ; Jeong, Myung-Il ; Chandra, S. V Jagadeesh
Author_Institution :
Dept. of BIN Fusion Technol., Chonbuk Nat. Univ., Jeonju, South Korea
Abstract :
We investigated structural and electrical properties of Ge and Si metal oxide semiconductor (MOS) devices with Pt/HfO2 gate stacks. Post-metallization annealing in O2 ambient reduced the accumulation capacitance more significantly in Si devices than in Ge devices due to the increase in the thickness of a low-k interfacial layer in-between the HfO2 film and Si substrate. Ge devices exhibited lower effective work function values for a Pt gate electrode than Si devices owing to the presence of a large number of positively-charged dipoles caused by strong Fermi level pinning at the Ge surface.
Keywords :
Fermi level; MIS devices; elemental semiconductors; germanium; hafnium compounds; platinum; silicon; Fermi level pinning; Ge; MOS devices; Pt-HfO2; Si; gate stacks; low-k interfacial layer; metal oxide semiconductor devices; positively-charged dipoles; post-metallization annealing; Annealing; Capacitance; Doping; Electrodes; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; Lead compounds; MOS devices; Temperature;
Conference_Titel :
Electrical Engineering/Electronics Computer Telecommunications and Information Technology (ECTI-CON), 2010 International Conference on
Conference_Location :
Chaing Mai
Print_ISBN :
978-1-4244-5606-2
Electronic_ISBN :
978-1-4244-5607-9
