Electrical and structural properties of ge metal-oxide-semiconductor devices with Pt/HfO2 gate stacks

We investigated structural and electrical properties of Ge and Si metal oxide semiconductor (MOS) devices with Pt/HfO₂ gate stacks. Post-metallization annealing in O₂ ambient reduced the accumulation capacitance more significantly in Si devices than in Ge devices due to the increase in the thickness of a low-k interfacial layer in-between the HfO₂ film and Si substrate. Ge devices exhibited lower effective work function values for a Pt gate electrode than Si devices owing to the presence of a large number of positively-charged dipoles caused by strong Fermi level pinning at the Ge surface.