An efficient VLSI architecture for discrete wavelet transform based on the daubechies architecture

A new basic architecture for one-dimensional discrete wavelet transform (1-D DWT) using Daubechies biorthogonal wavelet architecture is presented in this paper. The proposed DWT is composed of two independent FIR filters: a high-pass transposed form FIR filter and a low-pass transposed form FIR filter. The input to each filter is the same style as in the lifting scheme. Each FIR filter is a two-stage pipeline whose the fastest clock cycle is only either two adders delay or one multiplier delay. The proposed architecture has higher speed improved from Daubechies architecture, but uses less hardware resources. The area is further optimized by the RAG (Reduce Adder Graph) algorithm. Compare to the lifting scheme architecture which is commonly used, the proposed architecture achieves faster speed, shorter output latency, and the efficient pipeline architecture with simpler control.