An asymmetrical half-bridge forward converter with current doubler

This paper presents the analysis and design of an asymmetrical half-bridge forward converter with current doubler. This converter can minimize the switching power loss by realizing the zero-voltage-switching (ZVS) during the turn-on conditions. The principle of the converter operation is explained and analyzed. In order to achieve the ZVS conditions, the required interlock delay time between gate signals of two switches, the leakage transformer inductance is needed. The simulation results from a 30 V/20 A 80 kHz are also presented, which is used to verify the theoretical analysis.