DocumentCode :
52226
Title :
Utilizing Circuit Structure for Scan Chain Diagnosis
Author :
Wei-Hen Lo ; Ang-Chih Hsieh ; Chien-Ming Lan ; Min-Hsien Lin ; TingTing Hwang
Author_Institution :
Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Volume :
22
Issue :
12
fYear :
2014
fDate :
Dec. 2014
Firstpage :
2766
Lastpage :
2778
Abstract :
Scan chain diagnosis has become a critical issue to yield loss in modern technology. In this paper, we present a scan chain partitioning algorithm and a scan chain reordering algorithm to improve scan chain fault diagnosis resolution. In our scan chain partition algorithm, we take into consideration not only logic dependency but also the controllability between scan flip-flops. After the partition step, the ordering of scan cells is performed to decrease the range of suspect faulty scan cells by a bipartite matching reordering algorithm. The experimental results show that our method can reduce the number of suspect scan cells from 378-31 to at most 3 for most cases of ITC´99 benchmarks.
Keywords :
boundary scan testing; design for testability; fault diagnosis; flip-flops; integrated circuit yield; ITC´99 benchmarks; bipartite matching reordering algorithm; circuit structure; scan chain fault diagnosis resolution; scan chain partitioning algorithm; scan chain reordering algorithm; scan flip-flops; yield loss; Circuit faults; Controllability; Fault diagnosis; Inverters; Logic gates; Partitioning algorithms; Test pattern generators; Design for testability; digital circuits; fault diagnosis; fault diagnosis.;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2013.2294712
Filename :
6704833
Link To Document :
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