Low power FPGA design using hybrid CMOS-NEMS approach

Author

Yu Zhou ; Thekkel, S. ; Bhunia, Swarup

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Case Western Reserve Univ., Cleveland, OH, USA

fYear

2007

fDate

27-29 Aug. 2007

Firstpage

14

Lastpage

19

Abstract

Higher integration density of nanoscale CMOS causes two major design challenges in SRAM-based Field Programmable Gate Array (FPGA) designs: large power dissipation (contributed by both leakage and dynamic power) and reduced reliability of operation. In this paper, we propose a hybrid design approach for SRAM-based FPGA that can leverage on non-volatile carbon nanotube based nano electro-mechanical systems (NEMS) switches for low static and dynamic power. Simulations show that the proposed CMOS-NEMS lookup table (LUT) based circuits can achieve a reduction of up to 91% in total power at iso-performance, compared to the conventional CMOS-based LUT circuits.

Keywords

CMOS logic circuits; SRAM chips; carbon nanotubes; field programmable gate arrays; logic design; nanoelectromechanical devices; switches; table lookup; CMOS-based LUT circuits; SRAM; field programmable gate array designs; hybrid CMOS-NEMS approach; hybrid design approach; lookup table; low power FPGA design; nanoelectromechanical system switches; nanoscale CMOS; nonvolatile carbon nanotube; CMOS technology; Carbon nanotubes; Circuits; Costs; Field programmable gate arrays; Nanoelectromechanical systems; Nonvolatile memory; Power dissipation; Switches; Table lookup; FPGA design; hybrid CMOS-NEMS; low power;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design (ISLPED), 2007 ACM/IEEE International Symposium on

Conference_Location

Portland, OR

Electronic_ISBN

978-1-59593-709-4

Type

conf

DOI

10.1145/1283780.1283785

Filename

5514274