Title :
Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates
Author :
Myeong-Eun Hwang ; Seong-Ook Jung ; Roy, Kaushik
Author_Institution :
Purdue Univ., West Lafayette, IN, USA
Abstract :
We present a circuit delay framework in a closed form that accounts for the dynamic behavior of signal slope in subthreshold (VDD <; VT) as well as superthreshold (VDD > VT) regions. The proposed model converts a signal slope into its effective fanout for delay estimation. Simulations show that for ISCAS benchmark circuits, our framework exhibits a speedup of three orders of magnitude over HSPICE with 5%; error. Measured results in 65 nm show that for a wide range of interconnect lengths and geometries, the proposed model predicts the circuit delay with 5.7%; error at the supply voltage of VDD = 1.2V, and with 4.5% error at VDD = 0.4V.
Keywords :
CMOS logic circuits; SPICE; geometry; CMOS logic gates; HSPICE; ISCAS benchmark circuits; circuit delay framework; gate-interconnect interdependent delay model; interconnect lengths; slope interconnect effort; voltage 0.4 V; voltage 1.2 V; CMOS logic circuits; Circuit simulation; Delay estimation; Geometry; Integrated circuit interconnections; Length measurement; Logic gates; Predictive models; Semiconductor device modeling; Solid modeling; gate delay; interconnect; signal slope; subthreshold operation;
Conference_Titel :
Low Power Electronics and Design (ISLPED), 2007 ACM/IEEE International Symposium on
Conference_Location :
Portland, OR
Electronic_ISBN :
978-1-59593-709-4
DOI :
10.1145/1283780.1283865
