A low-power CSCD asynchronous viterbi decoder for wireless applications

Author

Kawokgy, M. ; Salama, C.A.T.

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada

fYear

2007

fDate

27-29 Aug. 2007

Firstpage

363

Lastpage

366

Abstract

This paper presents a 64-state, 1/2-rate asynchronous Viterbi decoder suitable for wireless and mobile applications. The decoder uses a novel dynamic Current Sensing Completion Detection (CSCD) technique and achieves significant power reduction while maintaining speed. The decoder, implemented in a 90 nm CMOS technology, occupies an area of 0.81 mm² and operates at 378 Mb/s while consuming 45 mW: a 43% power delay product improvement when compared to its synchronous counterpart.

Keywords

CMOS integrated circuits; Viterbi decoding; radiocommunication; 1/2-rate asynchronous Viterbi decoder; CMOS technology; current sensing completion detection technique; low-power CSCD asynchronous Viterbi decoder; wireless applications; Algorithm design and analysis; Application software; Arithmetic; CMOS logic circuits; CMOS technology; Decoding; Logic circuits; Logic design; Viterbi algorithm; Wireless sensor networks; asynchronous; current sensing completion detection; digital signal processing; handshaking; low-power; synchronous; viterbi; wireless;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design (ISLPED), 2007 ACM/IEEE International Symposium on

Conference_Location

Portland, OR

Electronic_ISBN

978-1-59593-709-4

Type

conf

DOI

10.1145/1283780.1283859

Filename

5514294