Constrained-random test bench for synthesis: Technique, tools and results

This paper presents the technique and tools for automatization of the synthesis of constrained-random test-bench for verification of the synthesizable designs of microprocessors and microcontrollers. The structure and parameters of constrained-random test-bench is coded by a stochastic grammar that is specified by elaborated tools. The Application, called RandGen, generates test-bench instantiation which is inserted in the design for synthesis. Also, elaborated tools allow to estimate various constrained-random parameters. The performed test experiments have showed that the apriori estimations and aposteriori test results are in good agreement.