Abstract :
Network-on-Chip (NoC) has emerged as a key architecture component that determines the overall performance, power, and area (PPA) of a contemporary System-on-Chip (SoC) device. The PPA characteristics of NoC are influenced by a wide range of issues, including semi-conductor technology (process node and corner, 2D/3D integration), circuit technology (synchronous, asynchronous), SoC architecture and use-case (number of IP blocks, general purpose or domain specific workload, frequency requirements, voltage, and clock domains), network topology (homogeneous, heterogeneous), routing strategy (deterministic, adaptive), router architecture and features (arity, virtual channels, Quality-of-Service, or QoS), and test architecture. Consequently, research in NoC design covers a wide gamut of topics. This special issue presents the latest advancements in NoC design and optimization.
