Compact modeling and robust layout optimization for contacts in deep sub-wavelength lithography

In this paper we propose a new equivalent contact resistance model which accurately calculates contact resistances from contact area, contact position, and contact shape. Based on the impact of contact resistance on the saturation current, we perform robust S/D contact layout optimization by minimizing the lithography variation as well as by maximizing the saturation current without any leakage penalty. The results on industrial 32nm node standard cells show up to 3.45% delay improvement under nominal process condition, 86.81% reduction in the delay variations between the fastest and slowest process corners.