Clock tree synthesis with pre-bond testability for 3D stacked IC Designs

This paper proposes comprehensive solutions to the clock tree synthesis problem that provides pre-bond testability for 3D IC designs. In 3D ICs, it is essential to stack only good dies by testing the individual dies before stacking. For the clock signaling, the pre-bond testing requires a complete 2D clock tree on each die. The previous work enables the pre-bond testability by allocating specially designed resources called TSV-buffers and redundant trees with transmission gates. We proposes viable solutions to the two fundamental problems of the previous work: (1) using much less buffer resources by preventing (potentially `bad´) TSV-buffers with a new tree topology generation algorithm; (2) completely removing the transmission gate control lines by using a specially designed component called self controlled clock transmission gate (SCCTG). Compared to the existing 3D tree topology generation algorithms, solution 1 can use 56%-88% less number of TSVs, 53%-67% less number of buffers, 22%-65% less total wirelength, and 26%-43% less clock power for the benchmark circuits with dense sink placements. Moreover, solution 2 reduces the total wirelength of all the benchmark circuits by 17% and 23% on average for the 2-die and 4-die stacked 3D ICs, respectively.