DocumentCode :
523928
Title :
Exploiting reconfigurability for low-cost in-situ test and monitoring of digital PLLs
Author :
Yin, Leyi ; Li, Peng
Author_Institution :
Dept. of ECE, Texas A&M Univ., College Station, TX, USA
fYear :
2010
fDate :
13-18 June 2010
Firstpage :
929
Lastpage :
934
Abstract :
We exploit the reconfigurability of recent all-digital PLL designs to provide novel in-situ output jitter test and diagnosis abilities under multiple parametric variations of key analog building blocks. Digital signatures are collected and processed under specifically designed loop filter configurations to facilitate low-cost high-accuracy performance prediction and diagnosis.
Keywords :
built-in self test; circuit noise; circuit testing; integrated circuit noise; jitter; mixed analogue-digital integrated circuits; phase locked loops; all digital PLL design reconfigurability; analog building blocks; digital signatures; in situ output jitter test; low cost in situ test; Built-in self-test; Circuit testing; Digital filters; Digital signatures; Jitter; Mathematical model; Monitoring; Permission; Phase noise; Semiconductor device noise; all-digital PLLs; diagnosis; mixed-signal BIST; online calibration; reconfiguration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (DAC), 2010 47th ACM/IEEE
Conference_Location :
Anaheim, CA
ISSN :
0738-100X
Print_ISBN :
978-1-4244-6677-1
Type :
conf
Filename :
5523426
Link To Document :
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