DocumentCode
523929
Title
A framework for optimizing thermoelectric active cooling systems
Author
Long, Jieyi ; Memik, Seda Ogrenci
fYear
2010
fDate
13-18 June 2010
Firstpage
591
Lastpage
596
Abstract
Thin-film thermoelectric cooling is a promising technology for mitigating heat dissipation in high performance chips. In this paper, we present an optimization framework for an active cooling system that is comprised of an array of thin-film thermoelectric coolers. We observe a set of constraints of the cooling system design. Firstly, integrating an excessive amount of coolers increases the chip package cost. Moreover, thermoelectric coolers are active devices, which dissipate heat in the chip package when they are in operation. Hence, setting the supply current level to operate the cooler improperly can actually lead to overheating of the chip package. Besides, the supply current needs to be delivered to the integrated cooler devices via dedicated pins. However, extra pins available on high-performance chip packages are limited. Observing these constraints, we propose an optimization framework for configuring the active cooling system, which minimizes the maximum silicon temperature. This includes determining the amount of coolers to deploy and their locations, the mapping of supply pins to the coolers, and determining the current levels of each pin. We propose algorithms to tackle the optimal configuration problem. We found that only a small portion of the silicon die needs to be covered by TEC devices (18% on average). Our experiments show that our algorithms are able to reduce the temperatures of the hot spots by as much as 10.6°C (compared to the cases without integrated thermoelectric coolers). The average temperature reduction is 8.6°C when 4 dedicated pins are available on the package. The total power consumption of the resulting active cooling system is reasonably small (~2 W). Our experiments also reveal that our framework maximizes the efficiency of the cooling devices. In the ideal case where hundreds of pins are available to tune the supply level of each individual cooler, the additional average reduction of the hot spot temperature is o- - nly 0.3°C.
Keywords
cooling; integrated circuit design; thermoelectric devices; chip package cost; heat dissipation; high-performance chip packages; hot spot temperature; maximum silicon temperature; optimal configuration problem; optimization framework; power consumption; supply current level; thermoelectric active cooling systems; thin-film thermoelectric cooling; Cooling; Costs; Current supplies; Packaging; Pins; Silicon; Temperature; Thermoelectric devices; Thermoelectricity; Transistors; Optimization; Thermal runaway; Thermoelectric cooling;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (DAC), 2010 47th ACM/IEEE
Conference_Location
Anaheim, CA
ISSN
0738-100X
Print_ISBN
978-1-4244-6677-1
Type
conf
Filename
5523429
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