DocumentCode :
524037
Title :
Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation
Author :
Zeng, Zhiyu ; Ye, Xiaoji ; Feng, Zhuo ; Li, Peng
Author_Institution :
Dept. of ECE, Texas A&M Univ., College Station, TX, USA
fYear :
2010
fDate :
13-18 June 2010
Firstpage :
831
Lastpage :
836
Abstract :
Integrating a large number of on-chip voltage regulators holds the promise of solving many power delivery challenges through strong local load regulation and facilitates system-level power management. The quantitative understanding of such complex power delivery networks (PDNs) is hampered by the large network complexity and interactions between passive on-die/package-level circuits and a multitude of nonlinear active regulators. We develop a fast combined GPU-CPU analysis engine encompassing several simulation strategies, optimized for various subcomponents of the network. Using accurate quantitative analysis, we demonstrate the significant performance improvement brought by on-chip low-dropout regulators (LDOs) in terms of suppressing high-frequency local voltage droops and avoiding the mid-frequency resonance caused by off-chip inductive parasitics. We perform comprehensive analysis on the tradeoffs among overhead of on-chip LDOs, maximum voltage droop and overall power efficiency. We conduct systematic design optimization by developing a simulation-based nonlinear optimization strategy that determines the optimal number of on-chip LDOs required and on-board input voltage, and the corresponding voltage droop and power efficiency for PDNs with multiple power domains.
Keywords :
circuit complexity; circuit optimisation; nonlinear programming; voltage regulators; GPU-CPU analysis; high-frequency local voltage droop suppression; local load regulation; midfrequency resonance; multiple power domains; network complexity; nonlinear active regulators; off-chip inductive parasitics; on-board input voltage; on-chip LDO; on-chip low-dropout regulators; on-chip voltage regulators; overall power efficiency; package-level circuits; passive on-die circuits; power delivery network optimisation; quantitative analysis; simulation-based nonlinear optimization strategy; system-level power management; systematic design optimization; Circuits; Design optimization; Energy management; Network-on-a-chip; Packaging; Performance analysis; Power system management; Regulators; System-on-a-chip; Voltage control; Power delivery network; low-dropout regulator; on-chip voltage regulation; power efficiency;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (DAC), 2010 47th ACM/IEEE
Conference_Location :
Anaheim, CA
ISSN :
0738-100X
Print_ISBN :
978-1-4244-6677-1
Type :
conf
Filename :
5523826
Link To Document :
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