• DocumentCode
    524078
  • Title

    Penalty for power reduction -: performance or schedule or yield?

  • Author

    Sarker, Bodhisatya ; Ahuja, Jaswinder ; Dutta, Arijit ; D., Srinath ; Sridhar, Kaip ; Nair, Radhakrishnan ; Lahiri, Jayant

  • Author_Institution
    Cadence Design Systems (I) Pvt Ltd, Delhi, India
  • fYear
    2008
  • fDate
    11-13 Aug. 2008
  • Firstpage
    303
  • Lastpage
    304
  • Abstract
    It is often said "It is always give and take" and that "there is no such thing as a free lunch". The same would hold true for Low Power designs. The questions oft asked is What are the trade-offs for reduction in power? What would be the limits of power reduction, before it starts impacting other parameters? Designs are generally characterized by four predominant parameters - performance, timing, area and power. As design and manufacturing became different disciplines supported by independent teams, two additional parameters were added to the design characterization, schedule and yield. Schedule implies the time taken to get the design to the desired performance and yield indicates the percentage of designs that meet the performance criterion, after manufacturing. Performance, schedule and yield have become a proxy for the expertise built in the design team and the capability of the tools to handle the complex designs. Teams with expertise and access to appropriate tools, can build high performance designs faster and at the desired yields. Traditionally performance has been correlated with timing or the maximum operating frequency of the design. More recently power is becoming an important area of concern, and is forcing designers to design within the power specifications of the design. Power has been seen as limiting the timing performance for many designs. In this key panel, we will discuss: What could be some of the best practices to reduce power while maintaining timing performanceHow could one analyze the performance, schedule, yield trade-off with an exampleDiscuss industry-wide effort to reduce the penalty for further power reduction
  • Keywords
    Application specific integrated circuits; Displays; Engineering management; Flash memory; Job shop scheduling; Manufacturing; Power engineering and energy; Power system management; Technology management; Timing; low power; performance; schedule; yield;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Low Power Electronics and Design (ISLPED), 2008 ACM/IEEE International Symposium on
  • Conference_Location
    Bangalore, India
  • Print_ISBN
    978-1-4244-8634-2
  • Electronic_ISBN
    978-1-60558-109-5
  • Type

    conf

  • DOI
    10.1145/1393921.1393999
  • Filename
    5529019