A 1.8/2.4-ghz dualband cmos low noise amplifier using miller capacitance tuning

Author

Balemarthy, Depak ; Paily, Roy

Author_Institution

Dept of Electron. & Commun. Eng., Indian Inst. of Technol., Guwahati, India

fYear

2008

fDate

11-13 Aug. 2008

Firstpage

295

Lastpage

300

Abstract

This paper describes an inductively source degenerated dual-band low noise amplifier (LNA) designed in a standard CMOS 0.18 μm TSMC process. The dual-band LNA can be tuned to 1.8-GHz and 2.4-GHz. The impedance matching is obtained at the required frequency bands using Miller-capacitance tuning. The designed LNA exhibits a gain of 18.2dB and 16.2dB and a noise figure of 5.0dB and 3.7dB at 1.8 and 2.4-GHz respectively. The LNA design is carried out using Mentor Graphics Eldo software.

Keywords

CMOS integrated circuits; capacitance; impedance matching; integrated circuit design; low noise amplifiers; CMOS TSMC process; Miller capacitance tuning; dual-band CMOS low noise amplifier; frequency 1.8 GHz; frequency 2.4 GHz; gain 16.2 dB; gain 18.2 dB; impedance matching; inductively source degenerated dual-band low noise amplifier; noise figure 3.7 dB; noise figure 5 dB; size 0.18 mum; CMOS process; Capacitance; Capacitors; Design engineering; Dual band; Frequency; Impedance matching; Low-noise amplifiers; Noise figure; Topology; dual-band LNA; gain; impedance matching; inductively source degenerated LNA; low noise amplifier (LNA); noise figure;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design (ISLPED), 2008 ACM/IEEE International Symposium on

Conference_Location

Bangalore

Print_ISBN

978-1-4244-8634-2

Electronic_ISBN

978-1-60558-109-5

Type

conf

DOI

10.1145/1393921.1393997

Filename

5529021