DocumentCode
524086
Title
Advances in low power verification
Author
Bergeron, Jarrah
Author_Institution
Synopsys Inc., Mountain View, CA, USA
fYear
2008
fDate
11-13 Aug. 2008
Firstpage
327
Lastpage
328
Abstract
Summary form only given. Low Power design has traditionally been the area of Implementation engineers. However, with more and more advanced SOCs having to adopt aggressive Power Management techniques, the verification of these architectures has become an explosive problem. This talk will focus on the basic technology shifts required in the arena of verification - in dynanamic, static and formal analysis, in the area of Verification Methodology, Languages and Protocols and in next generation automation flows. The talk will also highlight some of the unsolved problems of today´s technology and potential areas for research/collaboration between academia and industry.
Keywords
electronic engineering computing; formal verification; low-power electronics; program diagnostics; system-on-chip; SOC; dynanamic analysis; formal analysis; formal verification; implementation engineers; low power design; low power verification; next generation automation; power management techniques; protocols; static analysis; verification methodology; Analytical models; Automation; Collaboration; Computational modeling; Computer simulation; Design engineering; Energy management; Explosives; Power engineering and energy; Protocols; low power verification methodology;
fLanguage
English
Publisher
ieee
Conference_Titel
Low Power Electronics and Design (ISLPED), 2008 ACM/IEEE International Symposium on
Conference_Location
Bangalore
Print_ISBN
978-1-4244-8634-2
Electronic_ISBN
978-1-60558-109-5
Type
conf
DOI
10.1145/1393921.1393925
Filename
5529027
Link To Document