Title :
Clock gating for power optimization in ASIC design cycle theory & practice
Author :
Jairam, S. ; Rao, Madhav ; Srinivas, J. ; Vishwanath, Parimala ; Udayakumar, H. ; Rao, Jayasimha
Author_Institution :
SoC Center of Excellence, Texas Instrum., India
Abstract :
In this tutorial we present a comprehensive analysis of the available clock gate (CG) optimization approaches with re-cent innovations available in EDA tools as they have developed in time. Based on these approaches, we propose an integrated and additive design methodology spanning the backend design space. We show that over 30% power savings in dynamic power can be achieved through this methodology subject to application scenarios of the design.
Keywords :
application specific integrated circuits; clocks; energy conservation; logic gates; optimisation; ASIC design cycle theory; EDA tools; clock gating; dynamic power; power optimization; power savings; Application specific integrated circuits; Character generation; Clocks; Design methodology; Design optimization; Dynamic voltage scaling; Electronic design automation and methodology; History; Logic; Technological innovation; ASIC; RTL; SoC; low power; optimization;
Conference_Titel :
Low Power Electronics and Design (ISLPED), 2008 ACM/IEEE International Symposium on
Conference_Location :
Bangalore
Print_ISBN :
978-1-4244-8634-2
Electronic_ISBN :
978-1-60558-109-5
DOI :
10.1145/1393921.1394003
