Title :
Single stage static level shifter design for subthreshold to I/O voltage conversion
Author :
Yi-Shiang Lin ; Sylvester, Dennis M
Author_Institution :
Dept of EECS, Univ. of Michigan, Ann Arbor, MI, USA
Abstract :
A static subthreshold to I/O voltage level shifter is proposed. The proposed circuit employs a diode-connected pull-up transistor stack and a feedback structure to alleviate the drive strength requirement on the pull-down transistors. The proposed level shifter achieves less than 6 FO4 inverter delay under process and temperature variation when converting the input from 300 mV to 2.5 V. Compared to a conventional DCVS design, the new design consumes 8 times less power and is 10% faster under room temperature.
Keywords :
convertors; delay circuits; invertors; transistors; I-O voltage conversion; I-O voltage level shifter; diode-connected pull-up transistor stack; feedback structure; inverter delay; pull-down transistors; single stage static level shifter design; voltage 300 mV to 2.5 V; Delay; Diodes; Energy consumption; Feedback circuits; Inverters; Logic design; Low voltage; Permission; Switches; Temperature; level shifter; subthreshold;
Conference_Titel :
Low Power Electronics and Design (ISLPED), 2008 ACM/IEEE International Symposium on
Conference_Location :
Bangalore
Print_ISBN :
978-1-4244-8634-2
Electronic_ISBN :
978-1-60558-109-5
DOI :
10.1145/1393921.1393973
