DocumentCode
524095
Title
O2C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors
Author
Ghosh, Sudip ; Jung-Hwan Choi ; Ndai, P. ; Roy, Kaushik
Author_Institution
ECE, Purdue Univ., West Lafayette, IN, USA
fYear
2008
fDate
11-13 Aug. 2008
Firstpage
189
Lastpage
192
Abstract
In this paper, we propose O2C, a novel non-speculative adaptive thermal management technique that reduces the temperature during die-overheating using supply voltage scaling, while maintaining the rated clock frequency. This is accomplished by (a) scaling down the supply voltage, (b) isolating and predicting the set of critical paths, (c) ensuring (by design) that they are activated rarely, and (d) getting around occasional delay failures (at reduced voltage during die-overheating) in these paths by two-cycle operations (assuming all standard operations are single-cycle). Two-cycle operation is achieved by stalling the pipeline for extra clock cycles whenever the set of critical paths are activated. The rare two-cycle operation results in a small decrease in IPC (instructions per cycle). Since called O2C maintains the rated clock frequency and does not require pipeline stalling during supply voltage ramp-up/ramp-down, it achieves high throughput in a thermally constrained environment. We applied called O2C to the integer execution units of an in-order superscalar pipeline. Standard full-chip Dynamic Voltage-Frequency Scaling (DVFS) is very effective in bringing down the temperature, however; it is associated with large throughput loss due to pipeline stalling and slow operating frequency during thermal management. We integrated "O2C with standard DVFS" (called O2Cα) to demonstrate that it can act as a "first step" before full-scale thermal management is required. Our simulations indeed reveal that called O2Cα policy can avoid the requirement of full-scale DVFS during execution of programs.
Keywords
clocks; delays; microprocessor chips; DVFS; IPC; O2Cα; adaptive thermal management technique; delay failures; die-overheating; dynamic thermal management; full-chip dynamic voltage-frequency scaling; high-performance inorder microprocessors; inorder superscalar pipeline; instructions per cycle; integer execution units; occasional two-cycle operations; Clocks; Delay; Dynamic voltage scaling; Frequency; Logic; Microprocessors; Pipelines; Temperature; Thermal management; Throughput; adaptive clocking; adaptive thermal management; in-order processor;
fLanguage
English
Publisher
ieee
Conference_Titel
Low Power Electronics and Design (ISLPED), 2008 ACM/IEEE International Symposium on
Conference_Location
Bangalore
Print_ISBN
978-1-4244-8634-2
Electronic_ISBN
978-1-60558-109-5
Type
conf
DOI
10.1145/1393921.1393971
Filename
5529036
Link To Document