A secure and low-energy logic style using charge recovery approach

Author

Khatir, M. ; Moradi, Amir ; Ejlali, Alireza ; Manzuri Shalmani, M.T. ; Salmasizadeh, Mahmoud

Author_Institution

Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran, Iran

fYear

2008

fDate

11-13 Aug. 2008

Firstpage

259

Lastpage

264

Abstract

The charge recovery logic families have been designed several years ago not in order to eliminate the side-channel leakage but to reduce the power consumption. However, in this article we present a new charge recovery logic style not only to gain high energy efficiency but also to achieve the resistance against side-channel attacks especially against differential power analysis attacks. Our approach is a modified version of a classical charge recovery logic style namely 2N-2N2P. Simulation results show a significant improvement in DPA-resistance level as well as in power consumption reduction in comparison with 2N-2N2P and other DPA-resistant logic styles.

Keywords

logic design; power aware computing; power consumption; 2N-2N2P; DPA resistant logic styles; charge recovery logic families; low energy logic style; power consumption reduction; side channel leakage; Circuits; Computer security; Cryptography; Differential amplifiers; Energy consumption; Energy efficiency; Hardware; Logic design; Permission; Very large scale integration; cell level DPA-countermeasure; charge recovery logic; differential power analysis; side-channel attack;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design (ISLPED), 2008 ACM/IEEE International Symposium on

Conference_Location

Bangalore

Print_ISBN

978-1-4244-8634-2

Electronic_ISBN

978-1-60558-109-5

Type

conf

DOI

10.1145/1393921.1393990

Filename

5529043