Design of a Register Update Unit and a branch prediction unit of a microprocessor based on superscalar architecture using VLSI

In the field of microprocessors, speeds of processors doubles in every 18 months as, new microprocessors are always being designed using more and more advanced features. So, it´s always a challenge to design a new microprocessor with faster execution speed. This paper discusses about design of microarchitecture of superscalar processor using VLSI. This Proposed design is based on the rigorous research done through simulation of superscalar architecture using Simplescalar tool. The research was concentrated in three areas 1. Data dependence 2. Control dependence 3. Memory latency Various results were taken for several benchmarks in areas of operating system, database, and mathematics etc using `C´ language for different combinations of parameters. An optimum model was developed which would give a consistent performance in all the above areas. Among the three areas we are concentrating on the design of a Register Update Unit of Data dependence area and 1-level, 2-level branch prediction schemes of control dependence area. The units will be externally interfaced to an IP core through VLSI technique. By verifying the performance of the RUU and branch prediction unit using FPGA we are trying to find out an optimum unit for superscalar processor.