A post-processing approach to minimize TSV number for high-level synthesis of 3D ICs

3D IC technology stacks multiple integrated chips and its application is more and more popular. Therefore, developing CAD tools for the requirement of 3D architecture becomes urgent and important. In this paper, we present an integer linear programming (ILP) model for the application of resource layer assignment in high level synthesis. Our objective is to minimize the number of signal through-silicon-vias (TSVs) under both the layer number constraint and the footprint area constraint. Our approach has two possible applications: (1) a post-processing method to perform TSV number minimization for high-level synthesis of 3D ICs; (2) a post-processing method to transfer a design from 2D IC structure into 3D IC structure. Note that our approach guarantees minimizing the number of TSVs. Experimental data show that our approach works well in practice.