• DocumentCode
    525871
  • Title

    The influence of the layout on the ESD performance of HV-LDMOS

  • Author

    Lee, Jian-Hsing ; Su, Hung-Der ; Chan, Chien-Ling ; Yang, D.H. ; Chen, Jone F. ; Wu, K.M.

  • Author_Institution
    Technol. Dev. Div., Richtek Technol. Corp., Chubei, Taiwan
  • fYear
    2010
  • fDate
    6-10 June 2010
  • Firstpage
    303
  • Lastpage
    306
  • Abstract
    The root causes of the high voltage (HV) LDMOS (Fig. 2) failed at the low voltage electrostatic-discharge (ESD) zap is found. One is caused by the bulk layout and one is caused by the intrinsic characteristic of the device. From the findings, a new structure is proposed to eliminate the root causes without sacrificing the IV characteristics and dimension of the device.
  • Keywords
    electrostatic discharge; low-power electronics; power MOSFET; ESD performance; ESD zap; HV-LDMOS; bulk layout; high voltage LDMOS; low voltage electrostatic-discharge; Cities and towns; DH-HEMTs; Electrostatic discharge; Implants; Microelectronics; Power semiconductor devices; Research and development; Stress; Testing; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Power Semiconductor Devices & IC's (ISPSD), 2010 22nd International Symposium on
  • Conference_Location
    Hiroshima
  • ISSN
    1943-653X
  • Print_ISBN
    978-1-4244-7718-0
  • Electronic_ISBN
    1943-653X
  • Type

    conf

  • Filename
    5543900
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=525871